Conventionally, a PCCard.RTM. controller chip is connected between an ISA bus, PCI bus, or an EISA bus; and one or more PCCard.RTM. sockets. The selected bus and the sockets may be remote from each other, requiring a socket controller chip to be located either proximate to the socket or sockets or proximate to the selected bus. According to one conventional arrangement, if the socket controller chip is located proximate to a socket or sockets, then one or more cables are connected between the socket controller chip and the selected bus. According to another conventional arrangement, if the socket controller chip is located proximate to a selected bus, then the cables are connected between the socket controller chip and the socket or sockets. Such arrangements of the prior art are hampered by cross-talk between adjacent cables.
For example, when address or data information is applied to the bus, crosstalk may result to adjacent control signal lines, causing the control signals to change state and possibly resulting in a premature and erroneous read or write.
As is well known, the PCCard.RTM. standard is established by the Personal Computer Memory Card International Association (PCMCIA). The PCMCIA organization is a non-profit trade association founded in 1989 to define a standard memory card interface. The memory-only standard defines the current 68 pin physical interface. PC Card products are of particular significance in the portable and notebook computer markets, involving laptops and notebooks.
Typically, the number of lines required for the connection with the socket controller chip is greater than the number of lines in a single cable. Accordingly, two or more cables are connected in parallel, as for example shown in FIG. 1c.
The lines connecting with the socket controller chip include data lines, address lines, status lines, and control lines. In the case of two cables connecting with such lines, these cables will be physically adjacent to each other for all or some of the path between the socket controller chip and the connecting socket or selected bus.
Currently, in such parallel cable systems connecting with the socket controller chip, the cable lines are organized so that a data line in one cable may run adjacent a status or control line in the other cable line. Thus, data line transitions may reflect or spike during or near transitions and crosstalk into the adjacent status, interface, or control line or lines. Such crosstalk can disrupt or disable system operation.
It is desirable to prevent crosstalk, in a cost effective way, in physically adjacent lines of parallel cables, without use of shielding material or intervening conductive planes.